Maia is the first domain specific architecture
that integrates processors of different granularity (micro-processor, reconfigurable
Dataflow and FPGA); and is targeted towards the Voice Coding domain.
Compared with our
previous test chip, P1, Maia has a more sophisticated
synchronization scheme and more advanced address generator
which allow more complex kernels; it also has a micro-processor
which makes running an entire application possible.
This chip will be fabricated in 0.25u CMOS with
an estimated power dissipation of roughly 1mW at 1V supply voltage.
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Block
Diagram |
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Architecture
Features (includes info on handshaking & data
encoding) |
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Interconnect
Network |
